// SPDX-License-Identifier: GPL-2.0+
/*
 * Faraday MMC/SD Host Controller
 *
 * (C) Copyright 2010 Faraday Technology
 * Dante Su <dantesu@faraday-tech.com>
 *
 * Copyright 2018 Andes Technology, Inc.
 * Author: Rick Chen (rick@andestech.com)
 */

#include <clk.h>
#include <log.h>
#include <malloc.h>
#include <part.h>
#include <mmc.h>
#include <asm/global_data.h>
#include <linux/bitops.h>
#include <linux/io.h>
#include <linux/errno.h>
#include <asm/byteorder.h>
#include <faraday/ftsdc010.h>
#include "ftsdc010_mci.h"
#include <dm.h>
#include <dt-structs.h>
#include <errno.h>
#include <mapmem.h>
#include <pwrseq.h>
#include <syscon.h>
#include <linux/err.h>

#define CFG_CMD_TIMEOUT (CONFIG_SYS_HZ >> 2) /* 250 ms */
#define CFG_RST_TIMEOUT CONFIG_SYS_HZ /* 1 sec reset timeout */
//#define USE_FPGA_AE350

#ifdef USE_FPGA_AE350
typedef struct __attribute__ ((packed)) __attribute__((aligned(4)))
{
	volatile unsigned int	cmd;		/* 0x00 - command reg		*/
	volatile unsigned int	argu;		/* 0x04 - argument reg		*/
	volatile unsigned int	rsp0;		/* 0x08 - response reg0		*/
	volatile unsigned int	rsp1;		/* 0x0c - response reg1		*/
	volatile unsigned int	rsp2;		/* 0x10 - response reg2		*/
	volatile unsigned int	rsp3;		/* 0x14 - response reg3		*/
	volatile unsigned int	rsp_cmd;	/* 0x18 - responded cmd reg	*/
	volatile unsigned int	dcr;		/* 0x1c - data control reg	*/
	volatile unsigned int	dtr;		/* 0x20 - data timer reg	*/
	volatile unsigned int	dlr;		/* 0x24 - data length reg	*/
	volatile unsigned int	status;		/* 0x28 - status reg		*/
	volatile unsigned int	clr;		/* 0x2c - clear reg		*/
	volatile unsigned int	int_mask;	/* 0x30 - intrrupt mask reg	*/
	volatile unsigned int	pcr;		/* 0x34 - power control reg	*/
	volatile unsigned int	ccr;		/* 0x38 - clock contorl reg	*/
	volatile unsigned int	bwr;		/* 0x3c - bus width reg		*/
	volatile unsigned int	dwr;		/* 0x40 - data window reg	*/
	volatile unsigned int	feature;	/* 0x44 - feature reg		*/
	volatile unsigned int	rev;		/* 0x48 - revision reg		*/
}sdio_dev_t;


#define SDIO1   ((sdio_dev_t*)0xf8000000)

#define INLINE static inline

#define CMD_EN          (1<<9)
#define CMD_RST         (1<<10)
#define CMD_NEED_RSP    (1<<6)
#define CMD_LONG_RSP    (1<<7)
#define CMD_BUSY        (1<<31)

#define TIMEOUT_DAT     (1<<3)
#define TIMEOUT_RSP     (1<<2)

#define RECV_FIFO_NO_EMTY  (1<<9)
#define SEND_FIFO_FULL      (1<<8)

#define STATUS_RSP_CRC_OK       (1 << 4)
#define STATUS_DATA_CRC_OK      (1 << 5)
#define STATUS_DAT_END          (1 << 7)
#define STATUS_TIMEOUT          (3 << 2)
#define STATUS_CMD_SEND		    (1 << 6)
#define STATUS_SEND_FIFO_NOFULL (1 << 8)
#define STATUS_RECV_FIFO_NOEMTY (1 << 9)
#define STATUS_BUSY             (1 << 31)

#define DCR_FIFO_RST        (1<<10)

#define INLINE static inline
extern u8 crc7(u8 crc, const u8 *buffer, size_t len);
static uint32_t rsp_value[4];
INLINE int sdmc_cmd_send(void*sdio_reg,int cmd,uint32_t argu,uint32_t*rsp,int rsp_len){
	sdio_dev_t*sdio = (sdio_dev_t*)sdio_reg;
    while(sdio->status & CMD_BUSY);
    uint32_t r_v = CMD_EN | cmd;
    if(rsp){
        r_v |= CMD_NEED_RSP;
        if(rsp_len>2)
            r_v |= CMD_LONG_RSP;
    }
    sdio->argu = argu;
    sdio->cmd = r_v;
    int rsp_wait = 0;
    while(!(sdio->status & STATUS_CMD_SEND));rsp_wait++;
    //while(sdio->status & CMD_BUSY) rsp_wait++;
    if(rsp){
        rsp[0] = sdio->rsp0;
        rsp[1] = sdio->rsp1;
        if(rsp_len>2){
            rsp[2] = sdio->rsp2;
            rsp[3] = sdio->rsp3;
        }
    }
    return 0;
}

INLINE uint32_t _swap_(uint32_t value){
	return  (value>>24)|
			(((value>>16)&0xff)<<8)|
			(((value>>8 )&0xff)<<16)|
			(((value>>0 )&0xff)<<24);
}

INLINE int sdmc_rsp_get(void*sdio_reg,uint32_t*rsp,int len){
	sdio_dev_t*sdio = (sdio_dev_t*)sdio_reg;
	// if(!(sdio->status & FTSDC010_STATUS_RSP_CRC_OK)&&len<=2){
	// 	return 0;
	// }
	uint32_t crc_value = sdio->rev & 0xff;
	if(len>2){
		//需要效验数据
		rsp[3] = sdio->rsp3;
		rsp[2] = sdio->rsp2;
	}
	if(len>1){
		rsp[1] = sdio->rsp1;
		rsp[0] = sdio->rsp0;
	}

	if(len>2){
		//136,需要额外计算,需要高低位切换,135:128	为第一个字节
		uint32_t rsp_swap[4];
		rsp_swap[0] = _swap_(rsp[3]);
		rsp_swap[1] = _swap_(rsp[2]);
		rsp_swap[2] = _swap_(rsp[1]);
		rsp_swap[3] = _swap_(rsp[0]);

		uint8_t c = crc7(0,((uint8_t*)rsp_swap)+1,15)*2|1;
		printf("crc:%08x,%08x,%08x,%08x:%02x,%02x\n",rsp[3],rsp[2],rsp[1],rsp[0],crc_value,c);
		return c==crc_value;
	}

	return 1;
}

INLINE int sdmc_acmd_send(void*sdio,int acmd,uint32_t argu,uint32_t*rsp,int rsp_len){
    //需要接收与回复
    sdmc_cmd_send(sdio,55,0,rsp,2);
    return sdmc_cmd_send(sdio,acmd,argu,rsp,rsp_len);
}

INLINE void   sdmc_data_config(void*sdio_r,int data_en,int data_write,int fifo_rst){
	sdio_dev_t*sdio = (sdio_dev_t*)sdio_r;
    uint32_t v = data_en?(1<<6):0;
    v |= data_write?(1<<4):0;
    v |= fifo_rst  ?(1<<10):0;
    sdio->dcr = v;
}

#endif

#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct ftsdc010 {
	fdt32_t		bus_width;
	bool		cap_mmc_highspeed;
	bool		cap_sd_highspeed;
	fdt32_t		clock_freq_min_max[2];
	struct phandle_2_cell	clocks[4];
	fdt32_t		fifo_depth;
	fdt32_t		reg[2];
};
#endif

struct ftsdc010_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
	struct ftsdc010 dtplat;
#endif
	struct mmc_config cfg;
	struct mmc mmc;
};

struct ftsdc_priv {
	struct clk clk;
	struct ftsdc010_chip chip;
	int fifo_depth;
	bool fifo_mode;
	u32 minmax[2];
};


static inline int ftsdc010_send_cmd(struct mmc *mmc, struct mmc_cmd *mmc_cmd)
{
	struct ftsdc010_chip *chip = mmc->priv;
	struct ftsdc010_mmc __iomem *regs = chip->regs;
	int ret = -ETIMEDOUT;
	uint32_t ts, st;
	uint32_t cmd   = FTSDC010_CMD_IDX(mmc_cmd->cmdidx);
	uint32_t arg   = mmc_cmd->cmdarg;
	uint32_t flags = mmc_cmd->resp_type;

	cmd |= FTSDC010_CMD_CMD_EN;

	if (chip->acmd) {
		cmd |= FTSDC010_CMD_APP_CMD;
		//chip->acmd = 0;
	}

	if (flags & MMC_RSP_PRESENT)
		cmd |= FTSDC010_CMD_NEED_RSP;

	if (flags & MMC_RSP_136)
		cmd |= FTSDC010_CMD_LONG_RSP;

	writel(FTSDC010_STATUS_RSP_MASK | FTSDC010_STATUS_CMD_SEND,
		&regs->clr);
	if((cmd&0x3f)==41){
		arg |= 1<<30;
	}
	writel(arg, &regs->argu);
	writel(cmd, &regs->cmd);

	if (!(flags & (MMC_RSP_PRESENT | MMC_RSP_136))) {
		while(readl(&regs->status) & (1<<31));
		printf("cmd:%08x,%08x,%08x,%08x\n",cmd,readl(&regs->rsp0),arg,regs->status);
		for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
			if (readl(&regs->status) & FTSDC010_STATUS_CMD_SEND) {
				writel(FTSDC010_STATUS_CMD_SEND, &regs->clr);
				ret = 0;
				break;
			}
		}
	} else {
		st = 0;
		while(readl(&regs->status) & (1<<31));
		for (ts = get_timer(0); get_timer(ts) < CFG_CMD_TIMEOUT; ) {
			st = readl(&regs->status);
			writel(st & FTSDC010_STATUS_RSP_MASK, &regs->clr);
			if (st & FTSDC010_STATUS_RSP_MASK)
				break;
		}
		printf("cmd:%08x,%08x,%08x,%08x\n",cmd,readl(&regs->rsp0),arg,st);
		#ifdef USE_FPGA_AE350
		//136位不会带效验功能,只能自己效验
		if(!(MMC_RSP_PRESENT&flags)){
			return 0;
		}
		if(sdmc_rsp_get(regs,rsp_value,(flags & MMC_RSP_136)?4:2)){
			//成功
			if (flags & MMC_RSP_136) {
				mmc_cmd->response[0] = rsp_value[3];
				mmc_cmd->response[1] = rsp_value[2];
				mmc_cmd->response[2] = rsp_value[1];
				mmc_cmd->response[3] = rsp_value[0];
			} else {
				mmc_cmd->response[0] = rsp_value[0];
			}
			ret = 0;
		#else
		if (st & FTSDC010_STATUS_RSP_CRC_OK) {
			if (flags & MMC_RSP_136) {
				mmc_cmd->response[0] = readl(&regs->rsp3);
				mmc_cmd->response[1] = readl(&regs->rsp2);
				mmc_cmd->response[2] = readl(&regs->rsp1);
				mmc_cmd->response[3] = readl(&regs->rsp0);
			} else {
				mmc_cmd->response[0] = readl(&regs->rsp0);
			}

			ret = 0;
			#endif
		} else {
			debug("ftsdc010: rsp err (cmd=%d, st=0x%x)\n",
				mmc_cmd->cmdidx, st);
		}
	}
	if (ret) {
		debug("ftsdc010: cmd timeout (op code=%d)\n",
			mmc_cmd->cmdidx);
	} else if (mmc_cmd->cmdidx == MMC_CMD_APP_CMD) {
		chip->acmd = 1;
	}

	return ret;
}

static void ftsdc010_clkset(struct mmc *mmc, uint32_t rate)
{
	return;
	#ifndef USE_FPGA_AE350		//暂时不需要clkset
	struct ftsdc010_chip *chip = mmc->priv;
	struct ftsdc010_mmc __iomem *regs = chip->regs;
	uint32_t div;

	for (div = 0; div < 0x7f; ++div) {
		if (rate >= chip->sclk / (2 * (div + 1)))
			break;
	}
	chip->rate = chip->sclk / (2 * (div + 1));

	writel(FTSDC010_CCR_CLK_DIV(div), &regs->ccr);

	if (IS_SD(mmc)) {
		setbits_le32(&regs->ccr, FTSDC010_CCR_CLK_SD);

		if (chip->rate > 25000000)
			setbits_le32(&regs->ccr, FTSDC010_CCR_CLK_HISPD);
		else
			clrbits_le32(&regs->ccr, FTSDC010_CCR_CLK_HISPD);
	}
	#endif
}

static int ftsdc010_wait(struct ftsdc010_mmc __iomem *regs, uint32_t mask)
{
	int ret = -ETIMEDOUT;
	uint32_t st, timeout = 10000000;
	while (timeout--) {
		st = readl(&regs->status);
		if (!(st & mask))
			continue;
		writel(st & mask, &regs->clr);
		ret = 0;
		break;
	}

	if (ret){
		printf("ftsdc010: wait st(0x%x) timeout\n", mask);
	}

	return ret;
}

/*
 * u-boot mmc api
 */
static int ftsdc010_request(struct udevice *dev, struct mmc_cmd *cmd,
	struct mmc_data *data)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);
	int ret = -EOPNOTSUPP;
	uint32_t len = 0;
	struct ftsdc010_chip *chip = mmc->priv;
	struct ftsdc010_mmc __iomem *regs = chip->regs;

	if (data && (data->flags & MMC_DATA_WRITE) && chip->wprot) {
		printf("ftsdc010: the card is write protected!\n");
		return ret;
	}

	if (data) {
		uint32_t dcr;

		len = data->blocksize * data->blocks;

		/* 1. data disable + fifo reset */
		dcr = 0;
#ifdef CONFIG_FTSDC010_SDIO
		dcr |= FTSDC010_DCR_FIFO_RST;
#endif
#ifdef USE_FPGA_AE350
		//需要重启FIFO
		dcr |= FTSDC010_DCR_FIFO_RST;
#endif
		writel(dcr, &regs->dcr);

		/* 2. clear status register */
		writel(FTSDC010_STATUS_DATA_MASK | FTSDC010_STATUS_FIFO_URUN
			| FTSDC010_STATUS_FIFO_ORUN, &regs->clr);

		/* 3. data timeout (1 sec) */
		//printf("dtr:%d",chip->rate);
		if(chip->rate<1000){
			chip->rate = 100*1000*1000;
		}
		writel(chip->rate, &regs->dtr);

		/* 4. data length (bytes) */
		writel(len, &regs->dlr);

		/* 5. data enable */
		dcr = (ffs(data->blocksize) - 1) | FTSDC010_DCR_DATA_EN;
		if (data->flags & MMC_DATA_WRITE)
			dcr |= FTSDC010_DCR_DATA_WRITE;
		writel(dcr, &regs->dcr);
	}

	ret = ftsdc010_send_cmd(mmc, cmd);
	if (ret) {
		printf("ftsdc010: CMD%d failed\n", cmd->cmdidx);
		return ret;
	}

	if (!data)
		return ret;

	if (data->flags & MMC_DATA_WRITE) {
		const uint8_t *buf = (const uint8_t *)data->src;

		while (len > 0) {
			int wlen;

			/* wait for tx ready */
			ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_URUN);
			if (ret)
				break;

			/* write bytes to ftsdc010 */
			for (wlen = 0; wlen < len && wlen < chip->fifo; ) {
				writel(*(uint32_t *)buf, &regs->dwr);
				buf  += 4;
				wlen += 4;
			}

			len -= wlen;
		}

	} else {
		uint8_t *buf = (uint8_t *)data->dest;

		while (len > 0) {
			int rlen;

			/* wait for rx ready */
			ret = ftsdc010_wait(regs, FTSDC010_STATUS_FIFO_ORUN);
			if (ret)
				break;

			/* fetch bytes from ftsdc010 */
			for (rlen = 0; rlen < len && rlen < chip->fifo; ) {
				*(uint32_t *)buf = readl(&regs->dwr);
				buf  += 4;
				rlen += 4;
			}

			len -= rlen;
		}

	}

	if (!ret) {
		printf(",s:%08x",regs->status);
		ret = ftsdc010_wait(regs,
			FTSDC010_STATUS_DATA_END | FTSDC010_STATUS_DATA_CRC_OK);
	}

	return ret;
}

static int ftsdc010_set_ios(struct udevice *dev)
{
#ifdef USE_FPGA_AE350
	//直接切换成4线模式
	#if 0
	struct mmc *mmc = mmc_get_mmc_dev(dev);
	struct ftsdc010_chip *chip = mmc->priv;
	sdmc_acmd_send(chip->regs,6,2,rsp_value,2);
	#endif
#else
	struct mmc *mmc = mmc_get_mmc_dev(dev);
	struct ftsdc010_chip *chip = mmc->priv;
	struct ftsdc010_mmc __iomem *regs = chip->regs;

	ftsdc010_clkset(mmc, mmc->clock);

	clrbits_le32(&regs->bwr, FTSDC010_BWR_MODE_MASK);
	switch (mmc->bus_width) {
	case 4:
		setbits_le32(&regs->bwr, FTSDC010_BWR_MODE_4BIT);
		break;
	case 8:
		setbits_le32(&regs->bwr, FTSDC010_BWR_MODE_8BIT);
		break;
	default:
		setbits_le32(&regs->bwr, FTSDC010_BWR_MODE_1BIT);
		break;
	}

	return 0;
#endif
}

static int ftsdc010_get_cd(struct udevice *dev)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);
	struct ftsdc010_chip *chip = mmc->priv;
	struct ftsdc010_mmc __iomem *regs = chip->regs;
	//printf("status:%08x\n",regs->status);
	return (readl(&regs->status) & FTSDC010_STATUS_CARD_DETECT);
}

static int ftsdc010_get_wp(struct udevice *dev)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);
	struct ftsdc010_chip *chip = mmc->priv;
	struct ftsdc010_mmc __iomem *regs = chip->regs;
	if (readl(&regs->status) & FTSDC010_STATUS_WRITE_PROT) {
		printf("ftsdc010: write protected\n");
		chip->wprot = 1;
	}

	return 0;
}

static int ftsdc010_init(struct mmc *mmc)
{
	struct ftsdc010_chip *chip = mmc->priv;
	struct ftsdc010_mmc __iomem *regs = chip->regs;
	uint32_t ts;

	chip->fifo = (readl(&regs->feature) & 0xff) << 2;

	/* 1. chip reset */
	writel(FTSDC010_CMD_SDC_RST, &regs->cmd);
	#ifndef USE_FPGA_AE350		//暂时未实现
	for (ts = get_timer(0); get_timer(ts) < CFG_RST_TIMEOUT; ) {
		if (readl(&regs->cmd) & FTSDC010_CMD_SDC_RST)
			continue;
		break;
	}

	if (readl(&regs->cmd) & FTSDC010_CMD_SDC_RST) {
		printf("ftsdc010: reset failed\n");
		return -EOPNOTSUPP;
	}
	#else

	//wait busy end
	while(readl(&regs->cmd) & STATUS_BUSY);

	///////////////////////
	//不需要初始化流程
	//上电
	// uint32_t rsp[4];
	// while(sdio->status & STATUS_BUSY);     //等待操作完成

	// //CMD8,ACMD41
    // do{
    //     //CMD8,1aa
    //     sdmc_cmd_send(sdio,8,0x1aa,rsp,2);

    //     //ACMD41
    //     sdmc_acmd_send(sdio,41,(1<<30)|(0xff80<<8),rsp,2);
    // }while(!(rsp[0] & (1<<31)));       //初始化命令

	// //CMD2
    // sdmc_cmd_send(sdio,2,0,rsp,4);

	// //CMD3
    // sdmc_cmd_send(sdio,3,0,rsp,2);
    // uint32_t rca = rsp[0]>>16;

    // //CMD7
    // sdmc_cmd_send(sdio,7,rca<<16,rsp,2);
	// //ACMD6,4线模式
    // sdmc_acmd_send(sdio,6,2,rsp,2);
    // //完成初始化

	#endif

	/* 2. enter low speed mode (400k card detection) */
	ftsdc010_clkset(mmc, 400000);

	/* 3. interrupt disabled */
	writel(0, &regs->int_mask);

	return 0;
}

static int ftsdc010_probe(struct udevice *dev)
{
	struct mmc *mmc = mmc_get_mmc_dev(dev);
	return ftsdc010_init(mmc);
}

const struct dm_mmc_ops dm_ftsdc010_mmc_ops = {
	.send_cmd	= ftsdc010_request,
	.set_ios	= ftsdc010_set_ios,
	.get_cd		= ftsdc010_get_cd,
	.get_wp		= ftsdc010_get_wp,
};

static void ftsdc_setup_cfg(struct mmc_config *cfg, const char *name, int buswidth,
		     uint caps, u32 max_clk, u32 min_clk)
{
	cfg->name = name;
	cfg->f_min = min_clk;
	cfg->f_max = max_clk;
	cfg->voltages = //MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
		0x40ff8000;
	cfg->host_caps = caps;
	if (buswidth == 8) {
		cfg->host_caps |= MMC_MODE_8BIT;
		cfg->host_caps &= ~MMC_MODE_4BIT;
	} else {
		cfg->host_caps |= MMC_MODE_4BIT;
		cfg->host_caps &= ~MMC_MODE_8BIT;
	}
	cfg->part_type = PART_TYPE_DOS;
	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
}

static int ftsdc010_mmc_of_to_plat(struct udevice *dev)
{
	struct ftsdc_priv *priv = dev_get_priv(dev);
	struct ftsdc010_chip *chip = &priv->chip;

	if (CONFIG_IS_ENABLED(OF_REAL)) {
		chip->name = dev->name;
		chip->ioaddr = dev_read_addr_ptr(dev);
		chip->buswidth = dev_read_u32_default(dev, "bus-width", 4);
		chip->priv = dev;
		priv->fifo_depth = dev_read_u32_default(dev, "fifo-depth", 0);
		priv->fifo_mode = dev_read_bool(dev, "fifo-mode");
		if (dev_read_u32_array(dev, "clock-freq-min-max", priv->minmax, 2)) {
			if (dev_read_u32(dev, "max-frequency", &priv->minmax[1]))
				return -EINVAL;

			priv->minmax[0] = 400000;  /* 400 kHz */
		} else {
			debug("%s: 'clock-freq-min-max' property was deprecated.\n",
			      __func__);
		}
	}
	chip->sclk = priv->minmax[1];
	chip->regs = chip->ioaddr;

	return 0;
}

static int ftsdc010_mmc_probe(struct udevice *dev)
{
	struct ftsdc010_plat *plat = dev_get_plat(dev);
	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
	struct ftsdc_priv *priv = dev_get_priv(dev);
	struct ftsdc010_chip *chip = &priv->chip;
	struct udevice *pwr_dev __maybe_unused;

#if CONFIG_IS_ENABLED(OF_PLATDATA)
	int ret;
	struct ftsdc010 *dtplat = &plat->dtplat;
	chip->name = dev->name;
	chip->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
	chip->buswidth = dtplat->bus_width;
	chip->priv = dev;
	chip->dev_index = 1;
	memcpy(priv->minmax, dtplat->clock_freq_min_max, sizeof(priv->minmax));
	ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->clk);
	if (ret < 0)
		return ret;
#endif

	if (dev_read_bool(dev, "cap-mmc-highspeed") || \
		  dev_read_bool(dev, "cap-sd-highspeed"))
		chip->caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;

	ftsdc_setup_cfg(&plat->cfg, dev->name, chip->buswidth, chip->caps,
			priv->minmax[1] , priv->minmax[0]);
	chip->mmc = &plat->mmc;
	chip->mmc->priv = &priv->chip;
	chip->mmc->dev = dev;
	upriv->mmc = chip->mmc;
	return ftsdc010_probe(dev);
}

int ftsdc010_mmc_bind(struct udevice *dev)
{
	struct ftsdc010_plat *plat = dev_get_plat(dev);

	return mmc_bind(dev, &plat->mmc, &plat->cfg);
}

static const struct udevice_id ftsdc010_mmc_ids[] = {
	{ .compatible = "andestech,atfsdc010" },
	{ }
};

U_BOOT_DRIVER(ftsdc010_mmc) = {
	.name		= "ftsdc010_mmc",
	.id		= UCLASS_MMC,
	.of_match	= ftsdc010_mmc_ids,
	.of_to_plat = ftsdc010_mmc_of_to_plat,
	.ops		= &dm_ftsdc010_mmc_ops,
	.bind		= ftsdc010_mmc_bind,
	.probe		= ftsdc010_mmc_probe,
	.priv_auto	= sizeof(struct ftsdc_priv),
	.plat_auto	= sizeof(struct ftsdc010_plat),
};
